1. Technical Field
Embodiments of the present invention relate to an arbiter that can be used in a programmable logic device (PLD).
2. Related Art
Arbiters are typically implemented using logic of one type of PLD, a Field Programmable Gate Array (FPGA). As a non-limiting example of an arbiter, an FPGA can serve as a multi-port memory controller (MPMC) to control access to a DRAM memory from multiple devices. If processing or intelligence is used in the arbiter, such as a state machine based arbiter, the arbiter can become large very quickly. The intelligence of the arbiter made using components such as look up tables (LUTs) of the FPGA will grow in proportion to the amount of intelligence required. Increasing the resources used can adversely affect the maximum clock frequency the arbiter can operate if pipeline stages are not added. If pipeline states are added, the system performance, particularly latency, will be degraded.
An FPGA is an integrated circuit chip that includes components such as programmable input/output buffers (IOBs), configurable logic blocks (CLBs), block random access memory (BRAMs) and a programmable interconnect circuitry for interconnecting the IOBs, CLBs and BRAMs. The CLBs each include multiple LUTs that can be programmed to form logic elements such as AND, OR and XOR gates. The FPGAs further include SRAM configuration memory cells that can be programmed to configure the logic in the IOBs, CLBs and BRAMs. The SRAM configuration memory cells are typically programmed at startup of the FPGA, but can be reprogrammed using a partial reconfiguration process during operation of the FPGA by programming frames or a number of columns of the SRAM memory cells at a time.
It is desirable to efficiently use the components of a PLD, such as an FPGA, to develop an arbiter that can allow for complex arbitration algorithms, while still taking advantage of the dynamic reconfiguration abilities of the PLD and while maintaining low latency.